alkaid.codegen.rtl.vhdl package

Submodules

alkaid.codegen.rtl.vhdl.comb module

alkaid.codegen.rtl.vhdl.comb.comb_logic_gen(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None)

alkaid.codegen.rtl.vhdl.comb.output_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]])

alkaid.codegen.rtl.vhdl.comb.ssa_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]], print_latency: bool = False)

alkaid.codegen.rtl.vhdl.fsm module

alkaid.codegen.rtl.vhdl.fsm.fsm_logic_gen(fsm: FSM, name: str, print_latency=False, timescale: str | None = None, comb_logic_gen_fn=None, no_shreg: bool = False)

alkaid.codegen.rtl.vhdl.fsm.gen_io_map_sugar(precs: Sequence[Precision], direction: str, merge: bool)

alkaid.codegen.rtl.vhdl.fsm.generate_io_wrapper(fsm: FSM, module_name: str, timescale: str | None = None)

alkaid.codegen.rtl.vhdl.lookup module

alkaid.codegen.rtl.vhdl.lookup.lookup_source(combs: list[CombLogic]) → str

alkaid.codegen.rtl.vhdl.ternary module

alkaid.codegen.rtl.vhdl.ternary.ternary_line(sol: CombLogic, op_idx: int, kifs: Sequence[Precision], widths: Sequence[int]) → str

Module contents