alkaid.codegen.rtl.verilog package

Submodules

alkaid.codegen.rtl.verilog.comb module

alkaid.codegen.rtl.verilog.comb.comb_logic_gen(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None)

alkaid.codegen.rtl.verilog.comb.output_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]]) → list[str]

alkaid.codegen.rtl.verilog.comb.ssa_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]], print_latency: bool = False) → list[str]

alkaid.codegen.rtl.verilog.fsm module

alkaid.codegen.rtl.verilog.fsm.fsm_logic_gen(fsm: FSM, name: str, print_latency=False, timescale: str | None = '`timescale 1 ns / 1 ps', comb_logic_gen_fn=None, no_shreg: bool = False)

alkaid.codegen.rtl.verilog.fsm.gen_assignments(map_out: list[BitMap], name_inp: str, name_out: str, clocked: bool, inp_offset: str | None = None, out_offset: str | None = None)

alkaid.codegen.rtl.verilog.fsm.gen_assignments_conn(conn: Conn) → str

alkaid.codegen.rtl.verilog.fsm.gen_io_map_sugar(precs: Sequence[Precision], direction: str, merge: bool)

alkaid.codegen.rtl.verilog.fsm.gen_mux_assignments_conn(conn: Conn, enable_sig_name: str, dst_off: str | None) → list[str]

alkaid.codegen.rtl.verilog.fsm.generate_io_wrapper(fsm: FSM, module_name: str, timescale: str | None = '`timescale 1 ns / 1 ps')

alkaid.codegen.rtl.verilog.fsm.to_header(fsm: FSM, name: str, pad: bool)

alkaid.codegen.rtl.verilog.io_map module

class alkaid.codegen.rtl.verilog.io_map.BitMap(src, dst)

Bases: NamedTuple

can_merge(other: BitMap)

dst: tuple[int, int]: Alias for field number 1

merge(other: BitMap) → BitMap

src: tuple[int, int]: Alias for field number 0

alkaid.codegen.rtl.verilog.io_map.gen_io_map(precs0: Sequence[Precision], precs1: Sequence[Precision], merge: bool = False, bias0: int = 0, bias1: int = 0) → tuple[list[BitMap], tuple[int, int]]

alkaid.codegen.rtl.verilog.lookup module

alkaid.codegen.rtl.verilog.lookup.lookup_name(sol: CombLogic, op: Op) → str

alkaid.codegen.rtl.verilog.lookup.lookup_ops(sol: CombLogic) → list[Op]

alkaid.codegen.rtl.verilog.lookup.lookup_source(combs: list[CombLogic], timescale: str | None = None) → str

alkaid.codegen.rtl.verilog.lookup.table_hex(sol: CombLogic, op: Op) → list[str]

alkaid.codegen.rtl.verilog.ternary module

class alkaid.codegen.rtl.verilog.ternary.TernaryLayout(terms: tuple[alkaid.codegen.rtl.verilog.ternary.TernaryTerm, alkaid.codegen.rtl.verilog.ternary.TernaryTerm, alkaid.codegen.rtl.verilog.ternary.TernaryTerm], out_width: int, drop_lsbs: int)

Bases: object

drop_lsbs: int

out_width: int

terms: tuple[TernaryTerm, TernaryTerm, TernaryTerm]

class alkaid.codegen.rtl.verilog.ternary.TernaryTerm(addr: int, width: int, signed: int, negate: int, pad: int)