alkaid.codegen.rtl package

Subpackages

• alkaid.codegen.rtl.verilog package
  • Submodules
  • alkaid.codegen.rtl.verilog.comb module
    • comb_logic_gen()
    • gen_memfile()
    • get_table_name_memfile()
    • output_gen()
    • ssa_gen()
    • table_mem_gen()
  • alkaid.codegen.rtl.verilog.io_wrapper module
    • generate_io_wrapper()
    • hetero_io_map()
  • alkaid.codegen.rtl.verilog.pipeline module
    • pipeline_logic_gen()
  • Module contents
• alkaid.codegen.rtl.vhdl package
  • Submodules
  • alkaid.codegen.rtl.vhdl.comb module
    • comb_logic_gen()
    • output_gen()
    • ssa_gen()
  • alkaid.codegen.rtl.vhdl.io_wrapper module
    • generate_io_wrapper()
    • hetero_io_map()
  • alkaid.codegen.rtl.vhdl.pipeline module
    • pipeline_logic_gen()
  • Module contents

Submodules

alkaid.codegen.rtl.rtl_model module

class alkaid.codegen.rtl.rtl_model.RTLModel(comb_logic: CombLogic, path: str | Path, prj_name: str | None = None, flavor: str = 'verilog', n_stages: int = -1, latency_cutoff: float = -1, print_latency: bool = True, part_name: str = 'xcvu13p-flga2577-2-e', clock_period: float = 5, clock_uncertainty: float = 0.1, io_delay_minmax: tuple[float, float] = (0.2, 0.4))

Bases: object

compile(verbose=False, openmp=True, nproc: int | None = None, o3: bool = False, clean=True, metadata: None | dict[str, Any] = None, xls_opt: bool = False, no_shreg: bool = False)

Compile the generated code to a emulator for logic simulation.

Parameters:

• verbose (bool, optional) – Verbose output, by default False

• openmp (bool, optional) – Enable openmp, by default True

• nproc (int | None, optional) – Number of processes to use for compilation, by default None If None, will use the number of CPU cores, but not more than 32.

• o3 (bool | None, optional) – Turn on -O3 flag, by default False

• clean (bool, optional) – Remove obsolete shared object files and obj_dir, by default True

• metadata (dict[str, Any] | None, optional) – Additional metadata to write to metadata.json, by default None

• xls_opt (bool, optional) – Whether to apply XLS optimizations to the generated RTL. Requires xls-python package, only applicable to verilog codegen. Default is False.

• no_shreg (bool, optional) – Whether to add shreg_extract=”no” attribute to all pipeline registers in the generated RTL code. Default is False.

Raises:

RuntimeError – If compilation fails

predict(data: ndarray[tuple[Any, ...], dtype[floating]] | Sequence[ndarray[tuple[Any, ...], dtype[floating]]], n_threads: int = 0) → ndarray[tuple[Any, ...], dtype[floating]]

Run the model on the input data.

Parameters:

data (NDArray[np.floating]|Sequence[NDArray[np.floating]]) – Input data to the model. The shape is ignored, and the number of samples is determined by the size of the data. Must be float32 or float64; the output matches the input dtype.

Returns:

• NDArray[np.floating] – Output of the model in shape (n_samples, output_size), with the same dtype as data.

• n_threads (int, optional) – Number of threads to use for inference. If 0, will use all available threads, or the value of the DA_DEFAULT_THREADS environment variable if set. If < 0, OpenMP will be disabled. Default is 0.

write(metadata: None | dict[str, Any] = None, xls_opt: bool = False, no_shreg: bool = False)

Write the RTL project to the specified path.

Parameters:

• metadata (dict[str, Any] | None, optional) – Additional metadata to write to metadata.json, by default None

• xls_opt (bool, optional) – Whether to apply XLS optimizations to the generated RTL. Requires xls-python package, only applicable to verilog codegen. Default is False.

• no_shreg (bool, optional) – Whether to add shreg_extract=”no” attribute to all pipeline registers in the generated RTL code. Default is False.

class alkaid.codegen.rtl.rtl_model.at_path(path: str | Path)

Bases: object

alkaid.codegen.rtl.rtl_model.binder_gen(csol: Pipeline | CombLogic, module_name: str, II: int = 1)

alkaid.codegen.rtl.rtl_model.canon_name(name: str) → str

alkaid.codegen.rtl.rtl_model.get_io_kifs(sol: CombLogic | Pipeline)

alkaid.codegen.rtl.rtl_model.verilog_comb_logic_gen_xls(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None)

Module contents