alkaid.codegen.rtl package

Subpackages

• alkaid.codegen.rtl.verilog package
  • Submodules
  • alkaid.codegen.rtl.verilog.comb module
    • comb_logic_gen()
    • output_gen()
    • ssa_gen()
  • alkaid.codegen.rtl.verilog.fsm module
    • fsm_logic_gen()
    • gen_assignments()
    • gen_assignments_conn()
    • gen_io_map_sugar()
    • gen_mux_assignments_conn()
    • generate_io_wrapper()
    • to_header()
  • alkaid.codegen.rtl.verilog.io_map module
    • BitMap
      • BitMap.can_merge()
      • BitMap.dst
      • BitMap.merge()
      • BitMap.src
    • gen_io_map()
  • alkaid.codegen.rtl.verilog.lookup module
    • lookup_name()
    • lookup_ops()
    • lookup_source()
    • table_hex()
  • alkaid.codegen.rtl.verilog.ternary module
    • TernaryLayout
      • TernaryLayout.drop_lsbs
      • TernaryLayout.out_width
      • TernaryLayout.terms
    • TernaryTerm
      • TernaryTerm.addr
      • TernaryTerm.negate
      • TernaryTerm.pad
      • TernaryTerm.signed
      • TernaryTerm.width
    • ternary_layout()
    • ternary_line()
  • Module contents
• alkaid.codegen.rtl.vhdl package
  • Submodules
  • alkaid.codegen.rtl.vhdl.comb module
    • comb_logic_gen()
    • output_gen()
    • ssa_gen()
  • alkaid.codegen.rtl.vhdl.fsm module
    • fsm_logic_gen()
    • gen_io_map_sugar()
    • generate_io_wrapper()
  • alkaid.codegen.rtl.vhdl.lookup module
    • lookup_source()
  • alkaid.codegen.rtl.vhdl.ternary module
    • ternary_line()
  • Module contents

Submodules

alkaid.codegen.rtl.rtl_model module

class alkaid.codegen.rtl.rtl_model.RTLModel(logic: CombLogic | FSM, path: str | Path, prj_name: str | None = None, flavor: str = 'verilog', n_stages: int = -1, latency_cutoff: float = -1, print_latency: bool = True, part_name: str = 'xcvu13p-flga2577-2-e', clock_period: float = 5, clock_uncertainty: float = 0.1, io_delay_minmax: tuple[float, float] = (0.2, 0.4), ternary_fuse: bool = True)

Bases: object

canonicalize_inp_data(data: Mapping[str, ndarray] | Sequence[ndarray] | Sequence[Mapping[str, ndarray]] | ndarray) → dict[str, ndarray]

compile(verbose=False, openmp: bool = True, nproc: int | None = None, o3: bool = False, clean: bool = True, metadata: None | dict[str, Any] = None, xls_opt: bool = False, no_shreg: bool = False, _env: dict[str, str] | None = None)

eval()

get_port(name: str, dtype: Any = <class 'numpy.float64'>, scalar: bool = False)

property latency: float | None

predict(data: Mapping[str, ndarray] | Sequence[ndarray] | Sequence[Mapping[str, ndarray]] | ndarray, n_threads: int = 0, always_return_dict: bool = False) → dict[str, ndarray] | ndarray

property reg_bits: int

run(data: Mapping[str, ndarray] | Sequence[ndarray] | Sequence[Mapping[str, ndarray]] | ndarray, steps: int | None = None, scheduled: bool | None = None, output_only: bool = True, extra_steps: int = 0, n_threads: int = 1) → dict[str, ndarray]

set_port(name: str, values: Any, dtype: Any | None = None)

soft_reset()

property t: int

tick()

write(metadata: None | dict[str, Any] = None, xls_opt: bool = False, no_shreg: bool = False)

alkaid.codegen.rtl.rtl_model.fsm_config_gen(fsm: FSM, module_name: str) → str

alkaid.codegen.rtl.rtl_model.verilog_comb_logic_gen_xls(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None)

Module contents