alkaid.stateful package

Submodules

alkaid.stateful.fsm module

class alkaid.stateful.fsm.Buffer(sig: Signal, dtype=<class 'numpy.float64'>): Bases: ndarray

class alkaid.stateful.fsm.Conn(src: alkaid.stateful.fsm.Signal, dst: alkaid.stateful.fsm.Signal, enable_if: alkaid.stateful.fsm.Signal | None = None, alt_src: alkaid.stateful.fsm.Signal | None = None)

Bases: object

alt_src: Signal | None = None

property clocked: bool

dst: Signal

enable_if: Signal | None = None

classmethod from_dict(d: dict) → Conn

src: Signal

to_dict() → dict

class alkaid.stateful.fsm.Dir(*values)

Bases: Enum

IN = 1

INTERNAL = 0

OUT = -1

class alkaid.stateful.fsm.FSM(logic: dict[str, CombLogic], conns: tuple[Conn, ...], _sorted=False)

Bases: object

Finite State Machine representation with combinational logic and register connections.

classmethod from_dict(d: dict, raw: bool = False) → FSM

property inp_signals: tuple[Signal, ...]

property internal_signals: tuple[Signal, ...]

classmethod load(path: str | Path): Load from a JSON file; accepts gzip (detected by magic bytes).

property out_signals: tuple[Signal, ...]

predict(data: Mapping[str, ndarray] | Sequence[ndarray] | Sequence[Mapping[str, ndarray]] | ndarray) → dict[str, ndarray]

property regs: dict[str, Signal]

run(data: Mapping[str, ndarray] | Sequence[ndarray] | Sequence[Mapping[str, ndarray]] | ndarray, steps: int | None = None, scheduled: bool | None = None, output_only: bool = True, extra_steps: int = 0) → dict[str, ndarray]

save(path: str | Path, compresslevel: int = 6)

to_dict() → dict

property wires: dict[str, Signal]

class alkaid.stateful.fsm.FSMEmu(fsm: FSM)

Bases: object

canonicalize_inp_data(data: Mapping[str, ndarray] | Sequence[ndarray] | Sequence[Mapping[str, ndarray]] | ndarray) → dict[str, ndarray]

eval()

predict(data: Mapping[str, ndarray] | Sequence[ndarray] | Sequence[Mapping[str, ndarray]] | ndarray) → dict[str, ndarray]

run(data: Mapping[str, ndarray] | Sequence[ndarray] | Sequence[Mapping[str, ndarray]] | ndarray, steps: int | None = None, scheduled: bool | None = None, output_only: bool = True, extra_steps: int = 0) → dict[str, ndarray]

soft_reset()

tick()

class alkaid.stateful.fsm.ModuloSchedule(toggle: tuple[int, ...], period: int)

Bases: object

bias: int

check(t: int) → bool

property cum_valid_mask: tuple[int, ...]

dense_idx_to_t(idx: int) → int: idx-th valid step to t

n_valid_samples_between(t0: int, t1: int) → int: Number of valid steps between t0 (inclusive) and t1 (exclusive)

period: int

t_to_dense_idx(t: int) → int: t-th valid step to dense idx

to_list()

toggle: tuple[int, ...]

property valid_mask: tuple[bool, ...]

class alkaid.stateful.fsm.Signal(name: str, exposed: bool, precisions: tuple[Precision, ...] | tuple[tuple[bool | int, int, int], ...], rst_if: Signal | None = None, rst_to: tuple[float, ...] | tuple[int, ...] | None = None, reg: bool = True, schedule: ModuloSchedule | None = None, mode: str = '', view: tuple[int, int] | None = None, attrs: str | None = None, _dynamic_bias: tuple[Signal, int] | None = None)

Bases: object

property bitwidths: tuple[int, ...]

classmethod from_list(lst: list) → Signal

property jump_width: int

property precisions

property raw: Signal

read()

property rst_to

property size: int

to_list() → list

Serialize the signal to JSON-native types.

rst_if is stored by name; the reference is re-linked on load.

property view: tuple[int, int]

property width: int

write()

alkaid.stateful.ordering module

alkaid.stateful.ordering.topo_check_and_sort(conns: Sequence[Conn]) → list[Conn]

Order combinational connections so that every read happens after its write.

Each conn drives its dst view from up to three reads (src, alt_src, enable_if); the bit range of each is taken straight from the signal view (view_interval). A conn must run after every conn that drives a bit it reads, so the result is a topological order of the read-after-write dependency graph. The order within each disconnected subgraph is preserved; subgraphs may interleave freely.

Dependencies are tracked at interval granularity rather than per signal, so e.g. A[0:10] = B together with B[10:20] = A is not a loop – the bits do not overlap. Combinational-logic ports INTERNAL_name_inp / INTERNAL_name_outp are contracted into one node: every output bit is assumed to depend on every input bit, so reading any output bit waits on writing any input bit.

Raises:: ValueError – on a combinational loop, or a double assignment (two conns driving overlapping bits of the same signal).

alkaid.stateful package

Submodules

alkaid.stateful.fsm module

alkaid.stateful.ordering module

Module contents