da4ml.codegen.rtl.vhdl package

Submodules

da4ml.codegen.rtl.vhdl.comb module

da4ml.codegen.rtl.vhdl.comb.comb_logic_gen(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None)

da4ml.codegen.rtl.vhdl.comb.make_neg(signals: list[str], assigns: list[str], idx: int, qint: QInterval, v0_name: str, neg_repo: dict[int, tuple[int, str]])

da4ml.codegen.rtl.vhdl.comb.output_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]])

da4ml.codegen.rtl.vhdl.comb.ssa_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]], print_latency: bool = False)

da4ml.codegen.rtl.vhdl.io_wrapper module

da4ml.codegen.rtl.vhdl.io_wrapper.generate_io_wrapper(sol: CombLogic | Pipeline, module_name: str, pipelined: bool = False)

da4ml.codegen.rtl.vhdl.io_wrapper.hetero_io_map(qints: list[QInterval], merge: bool = False)

da4ml.codegen.rtl.vhdl.pipeline module

da4ml.codegen.rtl.vhdl.pipeline.pipeline_logic_gen(csol: Pipeline, name: str, print_latency=False, timescale: str | None = None, register_layers: int = 1)

Module contents