da4ml.codegen.rtl package

Subpackages

• da4ml.codegen.rtl.verilog package
  • Submodules
  • da4ml.codegen.rtl.verilog.comb module
    • comb_logic_gen()
    • gen_memfile()
    • get_table_name_memfile()
    • make_neg()
    • output_gen()
    • ssa_gen()
    • table_mem_gen()
  • da4ml.codegen.rtl.verilog.io_wrapper module
    • generate_io_wrapper()
    • hetero_io_map()
  • da4ml.codegen.rtl.verilog.pipeline module
    • pipeline_logic_gen()
  • Module contents
• da4ml.codegen.rtl.vhdl package
  • Submodules
  • da4ml.codegen.rtl.vhdl.comb module
    • comb_logic_gen()
    • make_neg()
    • output_gen()
    • ssa_gen()
  • da4ml.codegen.rtl.vhdl.io_wrapper module
    • generate_io_wrapper()
    • hetero_io_map()
  • da4ml.codegen.rtl.vhdl.pipeline module
    • pipeline_logic_gen()
  • Module contents

Submodules

da4ml.codegen.rtl.rtl_model module

class da4ml.codegen.rtl.rtl_model.RTLModel(solution: CombLogic | Pipeline, prj_name: str, path: str | Path, flavor: str = 'verilog', latency_cutoff: float = -1, print_latency: bool = True, part_name: str = 'xcvu13p-flga2577-2-e', clock_period: float = 5, clock_uncertainty: float = 0.1, io_delay_minmax: tuple[float, float] = (0.2, 0.4), register_layers: int = 1)

Bases: object

compile(verbose=False, openmp=True, nproc: int | None = None, o3: bool = False, clean=True, metadata: None | dict[str, Any] = None)

Compile the generated code to a emulator for logic simulation.

Parameters:

• verbose (bool, optional) – Verbose output, by default False

• openmp (bool, optional) – Enable openmp, by default True

• nproc (int | None, optional) – Number of processes to use for compilation, by default None If None, will use the number of CPU cores, but not more than 32.

• o3 (bool | None, optional) – Turn on -O3 flag, by default False

• clean (bool, optional) – Remove obsolete shared object files and obj_dir, by default True

• metadata (dict[str, Any] | None, optional) – Additional metadata to write to metadata.json, by default None

Raises:

RuntimeError – If compilation fails

predict(data: ndarray[tuple[Any, ...], dtype[_ScalarT]] | Sequence[ndarray[tuple[Any, ...], dtype[_ScalarT]]], n_threads: int = 0) → ndarray[tuple[Any, ...], dtype[float32]]

Run the model on the input data.

Parameters:

data (NDArray[np.floating]|Sequence[NDArray[np.floating]]) – Input data to the model. The shape is ignored, and the number of samples is determined by the size of the data.

Returns:

• NDArray[np.float64] – Output of the model in shape (n_samples, output_size).

• n_threads (int, optional) – Number of threads to use for inference. If 0, will use all available threads, or the value of the DA_DEFAULT_THREADS environment variable if set. If < 0, OpenMP will be disabled. Default is 0.

write(metadata: None | dict[str, Any] = None)

Write the RTL project to the specified path.

Parameters:

metadata (dict[str, Any] | None, optional) – Additional metadata to write to metadata.json, by default None

class da4ml.codegen.rtl.rtl_model.VHDLModel(solution: CombLogic | Pipeline, prj_name: str, path: str | Path, latency_cutoff: float = -1, print_latency: bool = True, part_name: str = 'xcvu13p-flga2577-2-e', clock_period: float = 5, clock_uncertainty: float = 0.1, io_delay_minmax: tuple[float, float] = (0.2, 0.4), register_layers: int = 1)

Bases: RTLModel

class da4ml.codegen.rtl.rtl_model.VerilogModel(solution: CombLogic | Pipeline, prj_name: str, path: str | Path, latency_cutoff: float = -1, print_latency: bool = True, part_name: str = 'xcvu13p-flga2577-2-e', clock_period: float = 5, clock_uncertainty: float = 0.1, io_delay_minmax: tuple[float, float] = (0.2, 0.4), register_layers: int = 1)

Bases: RTLModel

class da4ml.codegen.rtl.rtl_model.at_path(path: str | Path)

Bases: object

da4ml.codegen.rtl.rtl_model.binder_gen(csol: Pipeline | CombLogic, module_name: str, II: int = 1, latency_multiplier: int = 1)

da4ml.codegen.rtl.rtl_model.get_io_kifs(sol: CombLogic | Pipeline)

Module contents