da4ml.codegen.rtl.verilog package

Submodules

da4ml.codegen.rtl.verilog.comb module

da4ml.codegen.rtl.verilog.comb.comb_logic_gen(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None)

da4ml.codegen.rtl.verilog.comb.gen_memfile(sol: CombLogic, op: Op) → str

da4ml.codegen.rtl.verilog.comb.get_table_name_memfile(sol: CombLogic, op: Op) → tuple[str, str]

da4ml.codegen.rtl.verilog.comb.make_neg(lines: list[str], idx: int, qint: QInterval, v0_name: str, neg_repo: dict[int, tuple[int, str]])

da4ml.codegen.rtl.verilog.comb.output_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]]) → list[str]

da4ml.codegen.rtl.verilog.comb.ssa_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]], print_latency: bool = False) → list[str]

da4ml.codegen.rtl.verilog.comb.table_mem_gen(sol: CombLogic) → dict[str, str]

da4ml.codegen.rtl.verilog.io_wrapper module

da4ml.codegen.rtl.verilog.io_wrapper.generate_io_wrapper(sol: CombLogic | Pipeline, module_name: str, pipelined: bool = False)

da4ml.codegen.rtl.verilog.io_wrapper.hetero_io_map(qints: list[QInterval], merge: bool = False)

da4ml.codegen.rtl.verilog.pipeline module

da4ml.codegen.rtl.verilog.pipeline.pipeline_logic_gen(csol: Pipeline, name: str, print_latency=False, timescale: str | None = '`timescale 1 ns / 1 ps', register_layers: int = 1)

Module contents