da4ml.codegen.verilog package

Submodules

da4ml.codegen.verilog.comb module

da4ml.codegen.verilog.comb.comb_logic_gen(sol: Solution, fn_name: str, print_latency: bool = False, timescale: str | None = None)

da4ml.codegen.verilog.comb.output_gen(sol: Solution, neg_defined: set[int])

da4ml.codegen.verilog.comb.ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False)

da4ml.codegen.verilog.io_wrapper module

da4ml.codegen.verilog.io_wrapper.binder_gen(csol: CascadedSolution | Solution, module_name: str, II: int = 1, latency_multiplier: int = 1)

da4ml.codegen.verilog.io_wrapper.generate_io_wrapper(sol: Solution | CascadedSolution, module_name: str, pipelined: bool = False)

da4ml.codegen.verilog.io_wrapper.hetero_io_map(qints: list[QInterval], merge: bool = False)

da4ml.codegen.verilog.pipeline module

da4ml.codegen.verilog.pipeline.pipeline_logic_gen(csol: CascadedSolution, name: str, print_latency=False, timescale: str | None = '`timescale 1 ns / 1 ps', register_layers: int = 1)

da4ml.codegen.verilog.verilog_model module

class da4ml.codegen.verilog.verilog_model.VerilogModel(solution: Solution | CascadedSolution, prj_name: str, path: str | Path, latency_cutoff: float = -1, print_latency: bool = True, part_name: str = 'xcvu13p-flga2577-2-e', clock_period: float = 5, clock_uncertainty: float = 0.1, io_delay_minmax: tuple[float, float] = (0.2, 0.4), register_layers: int = 1)

Bases: object

compile(verbose=False, openmp=True, nproc: int | None = None, o3: bool = False, clean=True)

Compile the generated code to a emulator for logic simulation.

Parameters:

verbose (bool, optional) – Verbose output, by default False
openmp (bool, optional) – Enable openmp, by default True
nproc (int | None, optional) – Number of processes to use for compilation, by default None If None, will use the number of CPU cores, but not more than 32.
o3 (bool | None, optional) – Turn on -O3 flag, by default False
clean (bool, optional) – Remove obsolete shared object files, by default True

Raises:

RuntimeError – If compilation fails

predict(data: ndarray[tuple[int, ...], dtype[floating]])

Run the model on the input data.

Parameters:: data (NDArray[np.floating]) – Input data to the model. The shape is ignored, and the number of samples is determined by the size of the data.
Returns:: Output of the model in shape (n_samples, output_size).
Return type:: NDArray[np.float64]

write()

da4ml.codegen.verilog.verilog_model.get_io_kifs(sol: Solution | CascadedSolution)

Module contents

class da4ml.codegen.verilog.VerilogModel(solution: Solution | CascadedSolution, prj_name: str, path: str | Path, latency_cutoff: float = -1, print_latency: bool = True, part_name: str = 'xcvu13p-flga2577-2-e', clock_period: float = 5, clock_uncertainty: float = 0.1, io_delay_minmax: tuple[float, float] = (0.2, 0.4), register_layers: int = 1)